Sub-1A-Resolution Analysis and Physical Understanding of Gate/Insulator Interfacial Region in Scaled-Tinv High-k Gate Stacks

We propose sub-1Aring-order analysis of gate/insulator interfacial region in scaled-T_inv gate stacks by differentiating their C-V curves. By applying this technique to p⁺ poly-Si/HfSiON, it is found that gate depletion increases due to both lower poly impurity cone. (N_poly) and huge amount of pinning charge inside the dielectric (N_ox). We found ultra-thin SiN cap insertion recovers the degradation in N_poly and N_ox, leading to improvement of gate depletion and DeltaV_jb. By analyzing FUSI stacks, absence of semiconducting interlayer is verified with sub-1Aring resolution, and it is also found that As segregation outside SiO₂ leads to EOT increase as well as work function (WF) modulation in As-doped FUSI/SiO₂, whereas As segregation inside HfSiON results in smaller WF change in FUSI/HfSiON