Title :
Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs
Author :
Khellah, Muhammad ; Ye, Yibin ; Kim, Nam Sung ; Somasekhar, Dinesh ; Pandya, Gunjan ; Farhang, Ali ; Zhang, Kevin ; Webb, Clair ; De, Vivek
Author_Institution :
Circuits Res. Labs., Intel, Hillsboro, OR
Abstract :
Pulsed wordline (PWL) & pulsed bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15times while incurring <1% area overhead. Both PBL & PWL with read-modify-write (PWL-RMW) provide the best improvements (26times) in cell stability, with significant area overheads (4-8%)
Keywords :
CMOS memory circuits; SRAM chips; microprocessor chips; 0.7 V; 65 nm; CMOS technology; SRAM cell stability; area overheads; microprocessor designs; pulsed bitline; pulsed wordline; read-modify-write; CMOS digital integrated circuits; Circuit simulation; Circuit stability; Circuit testing; Microprocessors; Power generation; Pulse circuits; Random access memory; Space vector pulse width modulation; Voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705286
