Fast polylog-time reconfiguration of structurally fault-tolerant multiprocessors

We present a general methodology for the design of structurally k-fault-tolerant multiprocessors that can reconfigure quickly and in a distributed manner around any k processors faults. Structural fault tolerance is defined as the ability of the multiprocessor to reconfigure around faults in order to retain its original interconnection structure; this prevents any performance degradation when faults occur. The basic methodology used here is a generalization of the node covering approach that was introduced by Dutt and Hyes in (1992). The reconfiguration time of previous node-covering designs is linear in the number of processors, which, though faster than those of other designs, can be too slow for many application environments. In this paper, we present new types of node-covering designs that have configuration times T_R in the range {Θ(x log (N/x))}, where x is a design parameter that can range of 1 to N, and N is the number of processors. These designs also naturally present a hardware-cost to reconfiguration-time tradeoff; however, the extra hardware cost is nominal even for the fastest reconfiguring designs. We also suggest strategies for efficiently laying out these fast-reconfiguring designs in order to minimize the total wiring area