A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link

Author

O´Mahony, Frank ; Mansuri, Mozhgan ; Casper, Bryan ; Jaussi, James E. ; Mooney, Randy

Author_Institution

Intel Corp., Hillsboro, OR

fYear

0

fDate

0-0 0

Firstpage

29

Abstract

A 10GHz clock generation and distribution network for an 8-channel 20Gb/s/channel data transmitter is demonstrated in a 90nm 1.2V CMOS process. Jitter due to power supply and device noise is minimized with an LC VCO and repeaterless clock network. The performance of the forwarded-clock link degrades by only 4% due to plusmn5% supply noise at the transmitter. The LC VCO achieves supply noise sensitivity of 200MHz/V (0.02%-frequency/1%-supply noise) and short-term (8-symbol) rms jitter of 100fs. The clock distribution network delay sensitivity to supply noise is 36ps/V. The total clocking power is 408mW

Keywords

CMOS integrated circuits; clocks; integrated circuit noise; phase locked loops; timing jitter; voltage-controlled oscillators; 1.2 V; 10 GHz; 20 Gbit/s; 408 mW; 90 nm; CMOS technology; clock distribution network; clock generation network; data transmitter; device noise; phase locked loops; power supply noise; voltage-controlled oscillator; Bit error rate; Circuits; Clocks; Jitter; Phase locked loops; Power supplies; Repeaters; Transmitters; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705296

Filename

1705296