DocumentCode
2627098
Title
Performance effects of synchronization in parallel processors
Author
Chamberlain, Roger D. ; Franklin, Mark A.
Author_Institution
Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
fYear
1993
fDate
1-4 Dec 1993
Firstpage
611
Lastpage
616
Abstract
We investigate synchronization activities in application executing on distributed-memory MIMD architectures. Three applications are used to quantify the performance impact of synchronization as the number of processors is increased. We also investigate the performance improvement possible when synchronization is supported in hardware. The results show that significant performance improvement can be achieved. The hardware support should include barrier synchronization, operate-and-broadcast, and operations over subsets of processors
Keywords
distributed memory systems; parallel architectures; synchronisation; barrier synchronization; distributed-memory MIMD architectures; hardware support; operate-and-broadcast; parallel processors; performance impact; performance improvement; synchronization activities; Application software; Bars; Concurrent computing; Distributed computing; Global communication; Hardware; Iterative algorithms; Parallel algorithms; Parallel processing; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on
Conference_Location
Dallas, TX
Print_ISBN
0-8186-4222-X
Type
conf
DOI
10.1109/SPDP.1993.395478
Filename
395478
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