Title :
A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC
Author :
Järvinen, Jere A M ; Saukoski, Mikko ; Halonen, Kari
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo
Abstract :
This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); differential amplifiers; integrated circuit design; low-power electronics; operational amplifiers; 0.13 micron; 12 bit; 32 muW; ADC architecture; CMOS integrated circuit; algorithmic ADC; comparator; cyclic ADC; low-power electronics; operational amplifier; ratio-independent ADC; single differential amplifier; CMOS technology; Capacitance; Capacitors; Differential amplifiers; Latches; Operational amplifiers; Preamplifiers; Semiconductor device measurement; Very large scale integration; Voltage;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705305
