At-speed capture power reduction using layout-aware granular clock gate enable controls

Power consumption during the test mode of circuit operation is a major concern for scan based low power circuits. While there are multiple DFT and ATPG techniques proposed in the literature for addressing both shift and capture power reduction, most of the solutions are coarse-grained in nature - in the sense that they attempt to reduce power while being agnostic of the local power density in the power grid and its impact on the local dynamic IR Drop. Hence, such solutions can only fortuitously alleviate any local IR drop issues in the power grid, especially those arising from differences between functional and test mode use case scenarios. With clock gating being at the root of any dynamic power reduction solution in circuits today, it is not surprising that, power consumption during at-speed capture is strongly tied to a test pattern´s ability to enable or disable clock gates in the circuit (a key feature of all commercial ATPG tools today). In this paper, our work looks at clock gates critically from the following problem formulations (i) What DFT hooks can enable us to easily and selectively enable or disable clock gates?, (ii) how can DFT hooks be chosen in awareness of the local power density?, and (iii) with the DFT hooks in place, how can ATPG generate low power at-speed patterns with minimal impact on QoR (coverage/pattern count)? We share production solutions/methods developed to tackle the aforementioned problems in the context of a 45nm low power SoC taped out last year, along with various experimental results.