Fast BIST of I/O Pin AC specifications and inter-chip delays

The need for contactless testing of the input/output (I/O) delays in ICs is increasing. Contactless testing facilitates multi-site testing at wafer-sort and final test, known good die (KGD) for 2.5D/3D assemblies, and the use of lower cost ATE. We report results for a 28 nm technology, custom testchip with 2.5 Gb/s I/Os intended for 2.5D assemblies that was specifically designed for characterizing inter-chip delays. The IC has I/O built-in self-test (BIST) with 5~500 picosecond programmable resolution that measures delays via standard boundary scan without changes to the bidirectional I/O circuitry or the boundary scan cells. Based on lessons from the testchip, a modified version of the I/O circuitry was developed that permits measurement of classic ac specifications for I/Os, including data skew, setup/hold time, and data window for signals within the IC or from another IC. The modified I/O circuitry generally reduces I/O delay measurement time by one to two orders of magnitude relative to previously reported results.