• DocumentCode
    2627360
  • Title

    Impact of Layout on 90nm CMOS Process Parameter Fluctuations

  • Author

    Pang, Liang-Teck ; Nikolic, Borivoje

  • Author_Institution
    California Univ., Berkeley, CA
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    69
  • Lastpage
    70
  • Abstract
    A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC
  • Keywords
    CMOS digital integrated circuits; integrated circuit layout; integrated circuit testing; leakage currents; 90 nm; CMOS process; analog digital converter; digital circuit delay; digital circuit leakage; ring oscillator frequencies; test chip layout; transistor leakage; CMOS process; Circuit testing; Delay effects; Fingers; Fluctuations; Frequency measurement; Leakage current; Ring oscillators; Semiconductor device measurement; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    1-4244-0006-6
  • Type

    conf

  • DOI
    10.1109/VLSIC.2006.1705316
  • Filename
    1705316
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2627360