Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

Author

Yeung, Evelina ; Canagasaby, Karthisha ; Tripathi, Alok ; Chaudhuri, Santanu ; Meier, Pascal ; Prijic, James ; Joshi, Vivek ; Mazumder, Mohiuddin ; Dabral, Sanjay

Author_Institution

Intel Corp., Santa Clara, CA

fYear

0

fDate

0-0 0

Firstpage

79

Lastpage

80

Abstract

Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX clocking schemes are compared. The novel combination of voltage-mode driver (equalized or unequalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low-power option for short-distance links

Keywords

CMOS digital integrated circuits; current-mode circuits; driver circuits; equalisers; mobile communication; oscillators; phase locked loops; transceivers; 1.2 V; 1.6 to 9.6 Gbit/s; 90 nm; CMOS test chip; LC phase locked loop; RX clocking schemes; RX equalizers; TX equalizers; current-mode drivers; desktop I/O links; mobile I/O links; self-biased ring oscillator; server I/O links; voltage-mode drivers; Circuit testing; Clocks; Driver circuits; Equalizers; Packaging; Ring oscillators; Sampling methods; Sockets; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705321

Filename

1705321