Implementation of configurable hardware using wafer scale integration

In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed. In many ways wafer scale integration of large configurable hardware systems is very attractive for computational applications and this paper considers a wafer scale version of one particular configurable architecture: Configurable Array Logic (CAL) using CMOS