An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

Author

Wu, Ting ; Mayaram, Kartikeya ; Moon, Un-Ku

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

fYear

0

fDate

0-0 0

Firstpage

102

Lastpage

103

Abstract

A technique for reducing ring oscillator supply voltage sensitivity using on-chip calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with calibration circuitry is 0.064mm²

Keywords

CMOS integrated circuits; UHF oscillators; integrated circuit noise; jitter; phase locked loops; voltage-controlled oscillators; 0.13 micron; 0.5 to 2 GHz; 1 V; 10 mV; 19.4 ps; 4.4 ps; 9.4 mW; CMOS phase locked loop; VCO supply noise; on-chip calibration technique; ring oscillators; supply voltage sensitivity; voltage controlled oscillator; Calibration; Circuit noise; Energy consumption; Frequency measurement; Jitter; Noise measurement; Noise robustness; Phase locked loops; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705330

Filename

1705330