An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing ring oscillator supply voltage sensitivity using on-chip calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with calibration circuitry is 0.064mm²