DocumentCode :
2628019
Title :
A 7bit 800Msps 120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme
Author :
Makigawa, Kiyoshi ; Ono, Koichi ; Ohkawa, Takeshi ; Matsuura, Kouji ; Segami, Masahiro
Author_Institution :
Sony Corp., Kanagawa
fYear :
0
fDate :
0-0 0
Firstpage :
138
Lastpage :
139
Abstract :
A 7bit 800Msps folding and interpolation ADC is presented. This ADC uses new offset-averaging schemes in preamplifiers and current-mode interpolation stages and a digital-averaging scheme in a comparator stage to operate at higher speed with low power dissipation. The measured SNR is 36.8dB at a 200MHz input frequency. The prototype of the complete ADC is fabricated in a 90nm digital CMOS process and consumes 120mW with 2.5V and 1.2V supply
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; current-mode circuits; integrated circuit design; interpolation; 1.2 V; 120 mW; 2.5 V; 200 MHz; 7 bit; 90 nm; current-mode interpolation; digital CMOS process; digital-averaging scheme; folding ADC; interpolation ADC; mixed-averaging scheme; offset-averaging schemes; CMOS process; Circuits; Energy consumption; Frequency measurement; Interpolation; Parasitic capacitance; Power dissipation; Preamplifiers; Prototypes; Resistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
Type :
conf
DOI :
10.1109/VLSIC.2006.1705348
Filename :
1705348
Link To Document :
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