DocumentCode :
2628203
Title :
RICA: Reduced Interprocessor-Communication Architecture -concept and mechanisms
Author :
Sakai, Shuichi ; Matsuoka, Hiroshi ; Kodama, Yuetsu ; Sato, Mitsuhisa ; Shaw, Andrew ; Hirono, Hideo ; Okamoto, Kazuaki ; Yokota, Takashi
Author_Institution :
Real World Computing Partnership, Tsukuba, Ibaraki, Japan
fYear :
1993
fDate :
1-4 Dec 1993
Firstpage :
122
Lastpage :
125
Abstract :
One of the most significant issues in building general purpose massively parallel computers is the integration of computation and communication in an efficient and cost-effective manner. This paper presents a way of integrating computation and communication from the viewpoint of the processor architecture. It firstly states the concept of RICA, Reduced Interprocessor - Communication Architecture, which means the simplified and fused structure of communication and computation. Hardwired simple direct invocation of threads, and fusion of execution pipelines and message handling pipelines are the mechanisms for RICA
Keywords :
multiprocessor interconnection networks; parallel architectures; RICA; Reduced Interprocessor-Communication Architecture; execution pipelines; fused structure; general purpose massively parallel computers; hardwired simple direct thread invocation; message handling pipelines; processor architecture; Buildings; Clocks; Computer architecture; Concurrent computing; Data handling; Hardware; Laboratories; Network interfaces; Pipelines; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 1993. Proceedings of the Fifth IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-4222-X
Type :
conf
DOI :
10.1109/SPDP.1993.395542
Filename :
395542
Link To Document :
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