Title :
A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/
Author :
Markovic, Dejan ; Brodersen, Robert W. ; Nikolic, Borivoje
Author_Institution :
Berkeley Wireless Res. Center, California Univ., Berkeley, CA
Abstract :
An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band
Keywords :
CMOS integrated circuits; MIMO systems; application specific integrated circuits; minimisation; singular value decomposition; wireless LAN; 100 MHz; 16 MHz; 250 Mbit/s; 34 mW; 385 mV; 90 nm; ASIC; CMOS; SVD; baseband processing; multiantenna WLAN; multicarrier MIMO chip; singular value decomposition; CMOS technology; Circuits; Clocks; Iterative algorithms; MIMO; Matrix decomposition; Narrowband; Throughput; Voltage; Wireless LAN;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705358
