A self-tuning architecture for buck converters based on alternative test

This paper proposes a self-tuning architecture for buck converters based on a modified alternative “safe” testing approach. It avoids voltage spikes caused by conventional full load testing and provides measurements with strong statistical correlation with the DUT´s specifications. The measurements are sampled by a 5-bit ADC and analyzed by on-chip resources for evaluating the DUT specifications and predicting the corresponding values of buck converter tuning knobs to compensate for process variations when standard performances are not met. Thus, the proposed methodology enables self-test and self-tuning of buck converters during production test without the risk of DUT damage during standard production test. The causes of voltage spikes during conventional full load test are discussed both analytically and numerically and the working mechanism of an alternative test procedure is developed. This proposed technique is demonstrated through both simulation and hardware validation experiments.