Title :
A Register File with 8.4GHz Throughput for Efficient Instruction Scheduling in a Pentium~ 4 Processor
Author :
Nintunze, Novat ; Pham, Giao
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
This paper describes a unique register file (RF) for ping-pong operation in 65nm CMOS process. The merged ping-pong reduces array width by 50%, doubles the frequency of access, and allows for same phase read and write. Implementation as a dependency matrix allows for all read wordlines to be asserted at once. A bypass scheme merged with the bitline contributes to a 27% leakage saving
Keywords :
CMOS logic circuits; instruction sets; logic design; microprocessor chips; processor scheduling; 65 nm; 8.4 GHz; CMOS technology; Pentium 4 processor; bypass scheme; instruction scheduling; ping-pong operation; register file; Clocks; Logic design; Logic devices; Microprocessors; Phased arrays; Processor scheduling; Radio frequency; Read-write memory; Registers; Throughput;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705373
