Title :
A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers
Author :
Gondi, Srikanth ; Razavi, Behzad
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA
Abstract :
A merged equalizer/CDR circuit employs a parallel-path equalizer and triple-loop adaptation to achieve a binary data rate of 10 Gb/s. Realized in 0.13mum CMOS technology, the circuit adapts to FR4 trace lengths up to 24 inches with BER<10-13 while consuming 133 mW from a 1.6-V supply
Keywords :
CMOS integrated circuits; adaptive equalisers; radio links; radio receivers; 0.13 micron; 1.6 V; 10 Gbit/s; 133 mW; CMOS technology; clock and data recovery circuit; equalizer circuit; parallel-path equalizer; serial link receivers; triple-loop adaptation; Adaptive equalizers; Backplanes; Bandwidth; Bit error rate; CMOS technology; Circuits; Feedback; Frequency; Power dissipation; Transmitters;
Conference_Titel :
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0006-6
DOI :
10.1109/VLSIC.2006.1705376
