TSV-aware IDF-based power prediction for FPGA

In this paper, we present a new power prediction method with application in regular structures such as FPGAs. We will mainly discuss the effects of through-silicon-via (TSV) and interconnects in order to offer a robust IDF-based solution for power prediction problem. In our survey, we will show that TSV increases the average wire-length by up to 16 percent that in turn leads to 16 percent elevation in power consumption as well. The 3D TSV effect in wire-length is mapped into a 2D wire-length distribution. The wire-length distribution benefits an accurate continuous stochastic function. There is no need for layout extracted data as to power prediction. The error of prediction is systematic and will also decrease as the circuit size increases.