The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Author

Noda, Hideyuki ; Tanizaki, Tetsushi ; Gyohten, Takayuki ; Dosaka, Katsumi ; Nakajima, Masami ; Mizumoto, Katsuya ; Yoshida, Kanako ; Iwao, Takenobu ; Nishijima, Tetsu ; Okuno, Yoshihiro ; Arimoto, Kazutami

Author_Institution

Syst. Core Technol. Div., Renesas Technol. Corp., Hyogo

fYear

0

fDate

0-0 0

Firstpage

210

Lastpage

211

Abstract

A novel circuits and design methodology of the massively parallel processor based on the matrix architecture is introduced. Unique circuit design of the parallel fine-grained processing elements enhances the performance of MAC (multiply-accumulate) operation up to 30.0GOPS/W. Hierarchical memory architecture with super wide internal bus and distributed power management contribute to the enhancement of the processing efficiency and the robustness of the macro. The proposed circuit design methodology proposed in this paper is especially effective for realizing high-performance, robust processing macro employed in SOCs

Keywords

integrated circuit design; microprocessor chips; parallel processing; system-on-chip; MAC; SOC; circuit design methodology; distributed power management; hierarchical memory architecture; massively parallel processor; matrix architecture; robust design methodology; super wide internal bus; Circuit synthesis; Design methodology; Energy efficiency; Energy management; Engines; Memory architecture; Registers; Robustness; Signal processing algorithms; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705384

Filename

1705384