Scalable FFT processor for MIMO-OFDM based SDR systems

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of nontrivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 90Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8%, respectively.