Partitioning sequential circuits for logic optimization

Author

Dey, Sujit ; Brglez, Franc ; Kedem, G.

Author_Institution

Dept. of Comput. Sci., Duke Univ., Durham, NC, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

70

Lastpage

76

Abstract

The concepts of corolla partitioning based on an analysis of signal reconvergence to cyclic sequential circuits are extended. The sequential circuit is partitioned into corollas that will contain latches but can be peripherally retimed and resynthesized using combinational techniques. Cycles are broken in the circuit by ensuring that the partitions that are formed are acyclic. Application of the proposed partitioning, retiming and resynthesis approach to a set of large sequential benchmarks has shown considerable gains after resynthesis

Keywords

logic CAD; minimisation of switching nets; sequential circuits; acyclic partition; corolla partitioning; cyclic sequential circuits; logic optimization; resynthesis; retiming; sequential benchmarks; sequential circuit partitioning; signal reconvergence; Circuit synthesis; Clocks; Combinational circuits; Computer science; Latches; Logic design; Network synthesis; Pipelines; Sequential circuits; Signal analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139848

Filename

139848