Four-quadrant one-transistor-synapse for high-density CNN implementations

Author

Domínguez-Castro, R. ; Rodriguez-Vazquez, Angel ; Espejo, S. ; Carmona, R.

Author_Institution

Inst. de Microelectron., Seville Univ., Spain

fYear

1998

fDate

14-17 Apr 1998

Firstpage

243

Lastpage

248

Abstract

Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip

Keywords

CMOS analogue integrated circuits; analogue processing circuits; cellular neural nets; neural chips; CMOS technology; area occupation; cellular neural nets; general massively-parallel analog processors; linear four-quadrants electrically-programmable one-transistor synapse strategy; local connectivity; power dissipation; translationally-invariant processing arrays; Analog processing circuits; Artificial neural networks; CMOS process; CMOS technology; Cellular neural networks; Energy consumption; Power dissipation; Proposals; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications Proceedings, 1998 Fifth IEEE International Workshop on

Conference_Location

London

Print_ISBN

0-7803-4867-2

Type

conf

DOI

10.1109/CNNA.1998.685377

Filename

685377