Title :
A recursive fast multiplier
Author :
Danysh, Albert N. ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two´s complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.
Keywords :
digital arithmetic; logic design; multiplying circuits; architectural implementation; gate count; logic implementation; multiplier designs; random program; recursive fast multiplication algorithm; recursive fast multiplier; self-checking program; simulation program; speed; two´s complement signed multiplication; Algorithm design and analysis; Artificial intelligence; Counting circuits; Delay; Equations; Routing; Scalability;
Conference_Titel :
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5148-7
DOI :
10.1109/ACSSC.1998.750853
