DocumentCode
2630316
Title
Retiming of circuits with single phase transparent latches
Author
Shenoy, Yareiidra ; Brayton, Robert K. ; Sangiovanni-Vincentelli, A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
86
Lastpage
89
Abstract
An algorithm is developed for the retiming of single phase sequential circuits with level sensitive (transparent) latches. A set of constraints that permit retiming and optimal clock cycle computation are also developed. It is shown that a design with edge-triggered latches may be tested for speed-up using transparent latches
Keywords
circuit analysis computing; optimisation; sequential circuits; SIS; circuit functionality; circuit retiming; edge-triggered latches; level sensitive latches; optimal clock cycle computation; sequential interactive synthesis; single clock systems; single phase sequential circuits; single phase transparent latches; speed-up; Circuit testing; Circuit topology; Clocks; Delay; Equivalent circuits; Latches; Optimized production technology; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139850
Filename
139850
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