Modeling of interconnection lines for simulation of VLSI circuits

Author

dos Santos, F.S.G. ; Swart, Jacobus W.

Author_Institution

Sao Paulo Univ., Brazil

fYear

1991

fDate

14-16 Oct 1991

Firstpage

92

Lastpage

95

Abstract

A modeling approach for RC delays of interconnection lines, based on a lumped resistor and capacitor ladder, for the distributed RC transmission line, is presented. The interconnection line is considered to be driven by a MOS gate source, MOS gate loads, and RC interconnection branches. The minimum number of required RC sections is obtained for each case of driving an interconnection line and for a specified average relative error. Also, a rule based on the worst case of driving an interconnection branch in a complex RC tree network is proposed in order to automatically determine the recommended number of RC sections. This can be used as a first step before timing simulations

Keywords

VLSI; circuit analysis computing; delays; digital simulation; lumped parameter networks; MORI program; MOS gate loads; MOS gate source; RC delays; RC interconnection branches; RC tree network; VLSI circuits; average relative error; distributed RC transmission line; interconnection lines; lumped RC network; lumped resistor and capacitor ladder; timing simulations; Capacitance; Circuit simulation; Delay lines; Integrated circuit interconnections; Jacobian matrices; Large scale integration; SPICE; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139852

Filename

139852