Title :
A linear-array WSI architecture for improved yield and performance
Author :
Horst, Robert W.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when the configuration logic yield is above 75%. The architecture is shown to compare favorably to existing schemes in terms of performance, yield and overhead
Keywords :
VLSI; cellular arrays; fault tolerant computing; integrated circuit technology; microprocessor chips; parallel architectures; chain architecture; configuration logic yield; configuration scheme; fixed delay; four nearest neighbors; linear-array WSI architecture; overhead; partially defective wafer; performance; phase shifted synchronous clocking; yield; Computer architecture; Costs; Delay; High performance computing; Logic arrays; Pipelines; Registers; Routing; Spirals; Switches;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63887
