Title :
FPGA-based test bed for design and evaluation of low-power FIR-filter hardware accelerators
Author :
Walters, E. George, III ; Arner, Joshua J. ; Rojahn, Noah D.
Author_Institution :
Penn State Erie, Behrend Coll., Erie, PA, USA
Abstract :
Finite impulse response (FIR) filters are often used for processing audio, communication and other signals. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a test bed for low-power FIR-filter hardware accelerators that use truncated-matrix multipliers. It accepts analog input signals, filters them in real-time using an inexpensive field-programmable gate array (FPGA) development board, and produces analog outputs. The input is simultaneously processed using truncated-matrix multipliers and standard multipliers for comparison. Parameters such as filter coefficients, the number of unformed columns and the error correction method can be changed on the fly. The test bed enables real-time testing at the systems-integration level using real analog inputs and outputs.
Keywords :
FIR filters; analogue multipliers; field programmable gate arrays; low-power electronics; FPGA development board; FPGA-based test bed; analog input signal; field-programmable gate array; filter coefficient; finite impulse response filter; low-power FIR-filter hardware accelerator; real analog input; real analog output; real-time testing; standard multiplier; systems-integration level; truncated-matrix multiplier; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Logic gates; Registers; Standards; Very large scale integration;
Conference_Titel :
Consumer Electronics (ISCE), 2012 IEEE 16th International Symposium on
Conference_Location :
Harrisburg, PA
Print_ISBN :
978-1-4673-1354-4
DOI :
10.1109/ISCE.2012.6241684