Title :
A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process
Author :
Rashid, S. M Shahriar ; Ali, Sheikh Nijam ; Roy, Apratim ; Rashid, A.B.M.H.
Author_Institution :
Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
fDate :
March 31 2009-April 2 2009
Abstract :
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectra with 0.13 mum CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 V power supply. To the best of the authorspsila knowledge, a single stage LNA operating at such high frequency is yet to be reported.
Keywords :
CMOS integrated circuits; low noise amplifiers; CMOS process; Cadence Spectra; bandwidth 36.1 GHz; bandwidth 4.9 GHz; circuit simulation; gain 11.4 dB; passive output matching technique; power 3.38 mW; single stage low noise amplifier; size 0.13 mum; voltage 1.2 V; Bandwidth; CMOS process; Circuit noise; Circuit simulation; Frequency; Gain; Impedance matching; Low-noise amplifiers; Noise measurement; Power supplies; 0.13µm CMOS Process; 36.1 GHz; LNA; Low Noise Amplifier; Passive Output Matching; Single Stage;
Conference_Titel :
Computer Science and Information Engineering, 2009 WRI World Congress on
Conference_Location :
Los Angeles, CA
Print_ISBN :
978-0-7695-3507-4
DOI :
10.1109/CSIE.2009.86
