DocumentCode
2632074
Title
A 58–63.6GHz quadrature PLL frequency synthesizer using dual-injection technique
Author
Musa, Ahmed ; Murakami, Rui ; Sato, Takahiro ; Chaivipas, Win ; Okada, Kenichi ; Matsuzawa, Akira
Author_Institution
Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
fYear
2011
fDate
25-28 Jan. 2011
Firstpage
101
Lastpage
102
Abstract
This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of -96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply.
Keywords
CMOS integrated circuits; frequency synthesizers; injection locked oscillators; nanoelectronics; phase locked loops; phase noise; CMOS process; IEEE802.15.3c; dual-injection technique; frequency 60 GHz; frequency tripler; injection locked oscillator; phase noise; quadrature PLL frequency synthesizer; size 65 nm; CMOS integrated circuits; Frequency synthesizers; Phase locked loops; Phase noise; Synthesizers; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location
Yokohama
ISSN
2153-6961
Print_ISBN
978-1-4244-7515-5
Type
conf
DOI
10.1109/ASPDAC.2011.5722158
Filename
5722158
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