DocumentCode :
263219
Title :
Fault injection system for SEU emulation in Zynq SoCs
Author :
Villalta, Igor ; Bidarte, Unai ; Santos, Gorka ; Matallana, Asier ; Jimenez, Jaime
Author_Institution :
Dept. of Electron. & Telecommun., Univ. of the Basque Country UPV/EHU, Bilbao, Spain
fYear :
2014
fDate :
26-28 Nov. 2014
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents a fault injection method for SEU (Single Event Upset) emulation in FPGAs based on loading at the programmable logic a configuration file with an erroneous bit. A "Xilinx Zynq®-7000 All Programmable SoC" device has been used to implement it, which combines a hard microprocessor (Processing System PS) with Programmable Logic (PL). The emulation tool is fully implemented on the Zynq chip, which means that neither additional external equipment nor PCB modifications are needed. Communications to external devices that slow down the configuration process are avoided, so a high fault-injection rate is achieved. Previous works consider including fault injection circuitry at the PL. This circuitry can be affected by a faulty configuration file, leading the device to an unrecoverable state, which is named as "injection side effects". In the method proposed in this paper the injection is implemented in the processing system of the Zynq device, making the injection system independent to the programmable logic and avoiding the previously mentioned effect. This method allows using complete bitstreams, partial bitstreams and one-frame bitstreams to inject faults. A comparison is done so as to find the most appropriate bitstream type.
Keywords :
fault tolerance; field programmable gate arrays; radiation hardening (electronics); system-on-chip; FPGA; PL; SEU emulation; Xilinx Zynq-7000 all programmable SoC device; Zynq chip; complete bitstreams; configuration file; erroneous bit; external devices; fault-injection rate; hard microprocessor; injection side effects; one-frame bitstreams; partial bitstreams; processing system PS; programmable logic; single event upset emulation; Circuit faults; Computer architecture; Emulation; Field programmable gate arrays; Performance evaluation; Random access memory; Single event upsets; FPGA; SEU; ZYNQ; emulation; fault injection; fault tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on
Conference_Location :
Madrid
Type :
conf
DOI :
10.1109/DCIS.2014.7035579
Filename :
7035579
Link To Document :
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