Title :
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder
Author :
Osaki, Yuji ; Hirose, Tetsuya ; Kuroki, Nobutaka ; Numa, Masahiro
Author_Institution :
Dept. of Electr. & Electron. Eng., Kobe Univ., Kobe, Japan
Abstract :
A low-power current reference circuit was developed in a 0.35-μm standard CMOS process. The proposed circuit utilizes an offset-voltage generation subcircuit consisting of sub-threshold MOS resistor ladder and generates temperature compensated reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current, and that the total power dissipation was 586 nW. The temperature coefficient of the reference current can be kept small within 523ppm/°C in a temperature range from -20 to 100°C.
Keywords :
CMOS integrated circuits; reference circuits; resistors; CMOS current reference circuit; current 95 nA; offset voltage generation subcircuit; power 0.6 muW; power 586 nW; reference current; subthreshold MOS resistor ladder; Power supplies; Resistors; Temperature dependence; Temperature distribution; Temperature measurement; Transistors; Voltage measurement;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-7515-5
DOI :
10.1109/ASPDAC.2011.5722164
