Title :
Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designs
Author :
Pandini, Davide ; Scandelara, P. ; Guardian, Carlo
Author_Institution :
SGS-Thomson Microelectron., Agrate Brianza, Italy
Abstract :
A new fast and accurate methodology for crosstalk analysis of large VLSI IC interconnects is presented. In the proposed approach a reduced order approximation of the original interconnect network is derived by using a general application of the moment matching technique. Subsequently, a macromodel of the crosstalk voltage in the time domain is obtained, and a general method for a precise evaluation of the crosstalk voltage peak is described. Finally, the macromodel is used in order to evaluate the delay caused by crosstalk effects. The methodology described has been implemented in a sign-off tool that can be effectively used to evaluate crosstalk effects in signal integrity analysis of large digital circuits. Potentially hazardous circuit behavior caused by crosstalk can thus be detected without running massive time consuming circuit simulations. The effectiveness of our approach is demonstrated by application examples
Keywords :
VLSI; circuit analysis computing; crosstalk; integrated circuit interconnections; timing; VLSI IC interconnects; circuit simulations; coupled interconnects; crosstalk analysis; crosstalk voltage peak; functional verification; moment matching; reduced order approximation; reduced order macromodel; signal integrity analysis; sub-half-micron IC designs; time domain; timing; Capacitance; Coupling circuits; Crosstalk; Integrated circuit interconnections; Signal analysis; Timing; Transfer functions; Very large scale integration; Voltage; Wire;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669395
