Design of a GALS Wrapper for Network on Chip

Author

Ning, Wu ; Fen, Ge ; Fei, Wu

Author_Institution

Nanjing Univ. of Aeronaut. & Astronaut., Nanjing, China

Volume

3

fYear

2009

fDate

March 31 2009-April 2 2009

Firstpage

592

Lastpage

595

Abstract

In this paper, we present the design of a GALS wrapper used in Network on Chip (NoC) based on standard cells. The GALS wrapper includes two communication ports, 4-phase handshake circuits, data buffer and signal synchronizer. The detailed design methodology of GALS wrapper is given and the circuits are validated with Verilog-HDL and implemented in FPGA. The simulation results show that the wrapper provides fast and reliable asynchronous communication services for the subsystems working with different clocks in NoC.

Keywords

asynchronous circuits; buffer circuits; field programmable gate arrays; hardware description languages; logic design; network interfaces; network-on-chip; 4-phase handshake circuit; FPGA; GALS wrapper design; NoC subsystem working clock; Verilog-HDL; asynchronous communication service; communication port; data buffer; globally asynchronous locally synchronous style; network on chip; signal synchronizer; Asynchronous communication; Circuit simulation; Clocks; Computer buffers; Data communication; Logic circuits; Network-on-a-chip; Protocols; Switches; Synchronization; GALS; Handshake circuit; Network on Chip; Synchronizer;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Engineering, 2009 WRI World Congress on

Conference_Location

Los Angeles, CA

Print_ISBN

978-0-7695-3507-4

Type

conf

DOI

10.1109/CSIE.2009.520

Filename

5170909