Title :
Hardware implementation of an efficient correlator for Golay pairs derived from kernels of lengths 2, 10 and 26
Author :
Garcia, E. ; Perez, M.C. ; Hernandez, A. ; Urena, J. ; Garcia, J.J. ; Castilla, J.M. ; Lindo, A.
Author_Institution :
Dept. of Electron., Univ. of Alcala, Alcala de Henares, Spain
Abstract :
Golay complementary pairs have been widely used in signal coding and pulse compression systems due to the ideal sum of their aperiodic correlation functions. Furthermore, they can be used as basic building blocks for the generation of novel encoding schemes with zero correlation zones. In a recent work, algorithms for the efficient generation and correlation of Golay pairs obtained from kernels 2, 10 and 26 have been proposed. These pairs can adapt better the processing gain to the application requirements than previous ones based on power-of-two pairs. This work presents a new hardware implementation in configurable logic of an efficient correlator of Golay complementary pairs build from kernels 2, 10 and 26. This implementation allows real-time operation in cases in which high frequencies or long sequences are involved and can be easily adapted to the requirements of the application thanks to a set of generic parameters. This fast correlator, together with Golay code possibilities, make them a good choice for applications based on CDMA techniques, such as sonar, or wireless communications.
Keywords :
Golay codes; correlators; CDMA techniques; Golay code; Golay complementary pairs; aperiodic correlation functions; efficient correlator; encoding schemes; hardware implementation; pulse compression systems; signal coding; sonar; wireless communications; zero correlation zones; Correlation; Correlators; Delays; Field programmable gate arrays; Hardware; Kernel; Proposals; CDMA applications; FPGA-based implementation; Golay codes; efficient correlation;
Conference_Titel :
Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on
Conference_Location :
Madrid
DOI :
10.1109/DCIS.2014.7035588