A new LSI performance prediction model for interconnection analysis of future LSIs

Author

Takahashi, Shuji ; Edahiro, Masato ; Hayashi, Yoshihiro

Author_Institution

Silicon Syst. Res. Lab., NEC Corp., Sagamihara, Japan

fYear

1998

fDate

10-13 Feb 1998

Firstpage

51

Lastpage

56

Abstract

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clock-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds

Keywords

circuit analysis computing; delays; integrated circuit interconnections; large scale integration; LSI performance estimation; LSI performance prediction model; SUSPENS model; block cycle time; clock-skew model; delays; interconnection analysis; line delay; Clocks; Delay estimation; Electronic mail; Integrated circuit interconnections; Laboratories; Large scale integration; National electric code; Performance analysis; Predictive models; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-4425-1

Type

conf

DOI

10.1109/ASPDAC.1998.669396

Filename

669396