Parallel simulation of VHDL-AMS models

VHDL-AMS simulation is a compute intensive activity, particularly for large models, which motivates the development and use of approaches for accelerating the simulation process. An approach that is showing some promise is to execute the simulator in parallel on a distributed computer. The SEAMS VHDL-AMS simulator created at the University of Cincinnati exploits component-level partitioning, optimistic time synchronization, analog island modeling and a new discrete-analog time algorithm to completely partition the VHDL-AMS description at the entity-architecture level, and simulate the partitioned system on separate processors on a distributed computer. Results show significant speedups are possible