Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps

Linearized small-signal transistor models share the common circuit structure but may take different parameter values in the ac analysis of an analog circuit simulator. This property can be utilized for symbolic circuit analysis. This paper proposes to use a symbolic stamp for all device models in the same circuit for hierarchical symbolic analysis. Two levels of binary decision diagrams (BDDs) are used for maximum data sharing, one for the symbolic device stamp and the other for modified nodal analysis. The symbolic transadmittances of the device stamp share one BDD for storage saving. The modified nodal analysis (MNA) matrix formulated using symbolic stamp is of much lower dimension, hence it can be solved by a determinant decision diagram (DDD) with significantly reduced complexity. A circuit simulator is implemented based on the proposed partitioning architecture. It is able to analyze an op-amp circuit containing 44 MOS transistors exactly for the first time.