DocumentCode :
2632802
Title :
On the interplay of loop caching, code compression, and cache configuration
Author :
Rawlins, Marisha ; Gordon-Ross, Ann
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
fYear :
2011
fDate :
25-28 Jan. 2011
Firstpage :
243
Lastpage :
248
Abstract :
Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%.
Keywords :
cache storage; cache configuration; cache optimization techniques; cache tuning; code compression; decompression energy; loop caching; Benchmark testing; Energy consumption; Hardware; Optimization; Runtime; Software; Tuning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4244-7515-5
Type :
conf
DOI :
10.1109/ASPDAC.2011.5722191
Filename :
5722191
Link To Document :
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