Title :
Copper through silicon via (TSV) for 3D integration
Author :
Kothandaraman, C. ; Himmel, B. ; Safran, J. ; Golz, J. ; Maier, G. ; Farooq, M.G. ; Graves-Abe, T. ; Landers, W. ; Volant, R. ; Petrarca, K. ; Chen, F. ; Sullivan, T.D. ; LaRosa, G. ; Robson, N. ; Hannon, R. ; Iyer, S.S.
Author_Institution :
Semicond. R&D Center (SRDC), IBM, Hopewell Junction, NY, USA
Abstract :
Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no `Cu pumping´ or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.
Keywords :
CMOS integrated circuits; DRAM chips; copper; elemental semiconductors; integrated circuit reliability; silicon; thermal expansion; thermal management (packaging); three-dimensional integrated circuits; 3D integration; CMOS; Cu; Cu pumping; Si; TSV; copper; differential thermal expansion mismatch; functional 3D prototype; high K/metal gates; reliability; stacked embedded DRAM; through silicon via; Copper; Logic gates; Reliability; Silicon; Through-silicon vias; Wiring; 3D integration; TSV; stacked memories;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-1678-2
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2012.6241774
