DocumentCode
2633490
Title
Usage-based degradation of SRAM arrays due to bias temperature instability
Author
Bansal, Aditya ; Kim, Jae-Joon ; Rao, Rahul
Author_Institution
Thomas J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
fYear
2012
fDate
15-19 April 2012
Abstract
We propose a novel approach to estimate the workload based degradation of SRAM array stability with time due to NBTI (in PFETs) and PBTI (in NFETs). Goal is to obtain a realistic Vmin guard-band instead of optimistic (alternating stress) or pessimistic (static stress) assumptions. We also represent usage-based approach as stress-corner based approach to simplify the burn-in stress tests.
Keywords
SRAM chips; field effect transistors; NBTI; NFET; PBTI; PFET; SRAM array stability; SRAM arrays; alternating stress; bias temperature instability; burn-in stress tests; optimistic assumptions; pessimistic assumptions; realistic Vmin guard-band; static stress; usage-based degradation; workload based degradation; Benchmark testing; Degradation; FETs; Probability; Random access memory; Stress; Thermal stability;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2012 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4577-1678-2
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2012.6241799
Filename
6241799
Link To Document