Process combination to increase event granularity in parallel logic simulation

The increasing complexity of digital system designs is motivating a strong desire for higher capacity, faster simulation of logic circuits. While special purpose hardware accelerators show good performance, their high cost and long design times heave inhibited their widespread use. In contrast, the proliferation of reasonably priced symmetric multiprocessors provides an excellent platform upon which to build parallel logic simulators. Unfortunately, attempts to implement parallel simulators to speed logic simulation have meet with limited success. This is largely due to the low event granularity and high communication costs. Furthermore both empirical and analytical studies show that only limited parallelism exists within logic circuits for parallel simulators to exploit. Consequently, a reasonable alternative is to restructure the parallel processes, eliminating some by combining them into single tasks with larger event granularities and less expensive communication costs. This paper presents the constraints and method through which parallel logic gates in a VHDL description can be combined into single processes. Experimentally, we observed significant performance improvements; in some cases, process combination provided a speedup of 2.22 over the original, uncombined description