Title :
Multi-Mesh-an efficient topology for parallel processing
Author :
Das, Debasish ; Sinha, Bhabani P.
Author_Institution :
Electron. Unit, Indian Stat. Inst., Calcutta, India
Abstract :
This paper introduces a new interconnection scheme, called Multi-Mesh (MM) network, for parallel processing which uses multiple meshes as the basic building blocks interconnected in a suitable manner. The interconnection pattern is regular and suitable for VLSI implementation. Each processor in the network has degree four with a resulting diameter upper bounded by 2n for n4 processors. Routing can easily be done within 2n time on this network. Sum/minimum/maximum of n4 data values can be found in O(n) time. Two n×n matrices can be multiplied by the MM network in O(n 0.6) with an AT-cost of O(n3). The DFT of n sample points can be computed in O(n0.6) time on this network. Sorting of n3 data elements resident on n3 processors can be done in 2n log n+14n+o(n) time
Keywords :
communication complexity; matrix multiplication; multiprocessor interconnection networks; network routing; parallel architectures; sorting; MM network; Multi-Mesh network; VLSI implementation; data elements; diameter; interconnection pattern; interconnection scheme; matrices; multiple meshes; parallel processing; routing; topology; Broadcasting; Circuit topology; Computer architecture; Computer networks; Network topology; Parallel processing; Routing; Sorting; Upper bound; Wire;
Conference_Titel :
Parallel Processing Symposium, 1995. Proceedings., 9th International
Conference_Location :
Santa Barbara, CA
Print_ISBN :
0-8186-7074-6
DOI :
10.1109/IPPS.1995.395908