• DocumentCode
    2633729
  • Title

    Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation

  • Author

    Amaricai, Alexandru ; Boncalo, Oana

  • Author_Institution
    Univ. Politeh. of Timisoara, Timisoara, Romania
  • fYear
    2009
  • fDate
    27-29 Aug. 2009
  • Firstpage
    45
  • Lastpage
    49
  • Abstract
    Dedicated floating point units for divide-add fused operation (division followed by addition/subtraction) can be used to increase the performance of the interval Newton´s method. The key issue regarding these units is represented by the number of quotient bits generated. A high number leads to better accuracy, but also to low performance. The required number of quotient bits is determined by the exponents´ difference and the number of leading zeros. In this paper, we propose a divide-add fused unit which generates a variable number of quotient bits. This way, the latency for the cases when few quotient bits are needed is reduced, without loss in precision. Thus, the average performance of the divide-add fused operation is improved, while the area overhead is around 1%.
  • Keywords
    floating point arithmetic; addition; divide-add fused operation; floating point units; latency; quotient bits; subtraction; variable latency quotient generation; Costs; Delay; Design methodology; Digital systems; Energy consumption; Floating-point arithmetic; Hardware; Newton method; Nonlinear equations; Performance loss; digital arithmetic; divide-add fused; division; floating point arithmetic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on
  • Conference_Location
    Patras
  • Print_ISBN
    978-0-7695-3782-5
  • Type

    conf

  • DOI
    10.1109/DSD.2009.188
  • Filename
    5349981