An Effective Replacement Strategy of Cache Memory for an SMT Processor

An SMT processor is designed to execute multiple threads simultaneously in order to gain higher performance with sharing resources such as ALUs and cache memory among several threads. However, sharing cache memory may cause thread conflict misses which degrades its performance. In this paper, an effective replacement strategy in which conflicts miss ratio among threads is controlled by limiting the range of replaceable cache blocks is proposed and designed in order to overcome the problem on cache memory of an SMT processor. The proposed replacement strategy shows 5.3% as high performance in average and up to 41.9% in maximum as a conventional pseudo LRU strategy. Moreover, hardware costs for implementing the proposed strategy are reduced by 0.74% compared with pseudo LRU strategy.