An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs

Due to the multi-processor nature of Network Processors (NP), data packets entering the system are processed in parallel and might be transmitted out-of-order at the output leading to a significant degradation in network performance. In this paper we propose a new well-structured, area-efficient, and high speed hardware architecture for packet re-sequencing. For this purpose, several buffering techniques were investigated and analyzed in terms of complexity and memory requirements, taking into consideration the networking application and the impact of the number of processing elements (PE) on packet reordering. The proposed architecture, based on the appropriate buffering mechanism, is then demonstrated and implemented on our FPGA-based prototyping platform. In contrast to other solutions, our results showed 80% more efficient resource utilization while being capable to achieve 10% higher data rate of 3.2 Gbit/s.