• DocumentCode
    2634257
  • Title

    Minimizing the Impact of Scan Compression

  • Author

    Wohl, P. ; Waicukauski, J.A. ; Kapur, R. ; Ramnath, S. ; Gizdarski, E. ; Williams, T.W. ; Jaini, P.

  • Author_Institution
    Synopsys, Inc., Mountain View, CA
  • fYear
    2007
  • fDate
    6-10 May 2007
  • Firstpage
    67
  • Lastpage
    74
  • Abstract
    Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.
  • Keywords
    automatic test equipment; design for testability; area overhead; design for testability; scan compression; test generation flows; test time compressions; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Design for testability; Design methodology; Job shop scheduling; Pins; Silicon; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2007. 25th IEEE
  • Conference_Location
    Berkeley, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-2812-0
  • Type

    conf

  • DOI
    10.1109/VTS.2007.38
  • Filename
    4209893