Title :
Low Power Embedded Deterministic Test
Author :
Czysz, Dariusz ; Mrugalski, Grzegorz ; Rajski, Janusz ; Tyszer, Jerzy
Author_Institution :
Poznan Univ. of Technol.
Abstract :
This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.
Keywords :
automatic test pattern generation; design for testability; embedded systems; low-power electronics; automatic test pattern generation; design for testability; embedded deterministic test; hardware modification; industrial circuits; scan chains; switching activity; Automatic test pattern generation; Circuit testing; Design for testability; Graphics; Hardware; Integrated circuit technology; Logic design; Logic testing; Power dissipation; Switching circuits;
Conference_Titel :
VLSI Test Symposium, 2007. 25th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2812-0
DOI :
10.1109/VTS.2007.37
