Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit

Power-gate is a well-known technology used to decrease static (leakage) power consumption in low-power circuit currently. Several PMOS transistors are used as power switches (p-switches) to control the power source within the power-gating circuit. The p-switches are attached between the Vdd and the virtual Vdd power rail which served as the power source of circuit. The system of power management unit will turn off the power supply of the idle core by switching off the p-switches. As we know, the performance of a circuit depends on whether the supplied current is sufficient or not, and it relies on how much the channel width of p-switches could turn on simultaneously. Some defects will make the p-switches channel width diminished. The phenomenon of reducing channel width will not only affect the circuit performance but also cause chip reliability degrades because the current flow of p-switches overloaded. Therefore, it is important to diagnose/test the failed/defective p-switches. In this paper, the proposed CKVdd technique could easily identify the performance degradation caused by the failed/defective p-switches within the power-gating circuit.