• DocumentCode
    2634396
  • Title

    Mitigation technique against multi-bit-upset without area, performance and power overhead

  • Author

    Uemura, Taiki ; Tanabe, Ryo ; Matusyama, Hideya

  • Author_Institution
    Fujitsu Semicond. Ltd., Tokyo, Japan
  • fYear
    2012
  • fDate
    15-19 April 2012
  • Abstract
    In this work, we propose a technique for mitigating multi-bit-upset (MBU) which cannot be corrected by Error-Correction-Code (ECC) with using bit-line alternation and narrow deep-N-well. This technique mitigates MBU without area, performance and power overhead. The mitigation efficiency is evaluated with alpha and neutron acceleration experiments. The experimental results show excellent mitigation efficiency of the proposed technique.
  • Keywords
    SRAM chips; error correction codes; ECC; MBU mitigation; SRAM; bit-line alternation; error-correction-code; multibit-upset mitigation techniques; narrow deep-N-well; neutron acceleration; Acceleration; Error correction codes; Neutrons; Particle beams; Power demand; Random access memory; Sea level; ECC; MBU; Mitigation; SRAM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium (IRPS), 2012 IEEE International
  • Conference_Location
    Anaheim, CA
  • ISSN
    1541-7026
  • Print_ISBN
    978-1-4577-1678-2
  • Electronic_ISBN
    1541-7026
  • Type

    conf

  • DOI
    10.1109/IRPS.2012.6241846
  • Filename
    6241846